Circuit for voltage compensation in an electroluminescent display

ABSTRACT

A circuit for voltage compensation in an electroluminescent (EL) display is disclosed. The circuit includes a pixel unit of the EL display, an impedance load associated with the pixel unit and a switch. The pixel unit includes an electroluminescent (EL) device, a first capacitor configured to store a data associated with the EL device, and a transistor including a gate coupled to a first end of the first capacitor, and a first terminal coupled to a second end of the capacitor. The impedance load includes a second capacitor having a capacitance remarkably larger than that of the first capacitor. The switch selectively connects the pixel unit to a current sink via the impedance load.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. provisional application Ser. No. 62/421,435, filed Nov. 14, 2016, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

An electroluminescent (EL) display, such as an active matrix organic light emitting diode (AMOLED) display, may include an array of pixels. Each of the pixels may include an EL device, a switching transistor for transfer data that contains information on luminescence, and a driving transistor for driving the EL device to emit light according to the data. While such EL display enjoys the benefit of relatively low power consumption, display non-uniformity may exist among pixels due to process factors in semiconductor manufacturing. It may thus be desirable to have a circuit that solves the problem.

SUMMARY

Embodiments of the present invention provide a circuit for voltage compensation in an electroluminescent (EL) display. The circuit includes a pixel unit of the EL display, an impedance load associated with the pixel unit and a switch. The pixel unit includes an electroluminescent (EL) device, a first capacitor configured to store a data associated with the EL device, and a transistor including a gate coupled to a first end of the first capacitor, and a first terminal coupled to a second end of the capacitor. The impedance load includes a second capacitor having a capacitance remarkably larger than that of the first capacitor. The switch selectively connects the pixel unit to a current sink via the impedance load.

In an embodiment, the pixel unit further includes a transistor configured to reset a voltage level at the gate of the transistor during a first phase.

In another embodiment, the transistor is configured to receive a data associated with the EL device during a second phase.

In yet another embodiment, the second capacitor is configured to maintain a voltage level at the first terminal of the transistor in the second phase substantially identical to that in the first phase.

In still another embodiment, the pixel unit further includes another transistor configured to pass a current through the EL device during a third phase.

In yet still another embodiment, the second capacitor is configured to maintain a voltage difference between the gate and the first terminal of the transistor in the third phase substantially identical to that in the second phase.

In an embodiment, the current has a magnitude independent of the threshold voltage of the transistor.

In another embodiment, the pixel unit further includes another transistor configured to establish at the first terminal of the transistor a compensation voltage associated with a threshold voltage of the transistor during the first phase.

In still another embodiment, the another transistor includes a terminal, and the switch is configured to selectively connect the terminal to the current sink via the impedance load.

Some embodiments of the present invention provide an electroluminescent (EL) display that includes an array of pixel units and a circuit for voltage compensation for the pixel units. The circuit includes a pixel unit of the EL display, an impedance load associated with the pixel unit, and a switch. The pixel unit includes an electroluminescent (EL) device, a first capacitor configured to store a data associated with the EL device, and a transistor including a gate coupled to a first end of the first capacitor, and a first terminal coupled to a second end of the capacitor. The impedance load includes a second capacitor having a capacitance remarkably larger than that of the first capacitor. The switch selectively connects the pixel unit to a current sink via the impedance load.

Embodiments of the present invention also provide a method of voltage compensation in an electroluminescent (EL) display that comprises an array of pixel units each including an EL device, a transistor and a first capacitor. The method comprises providing a switch to selectively connect one of the pixel units to a current sink via an impedance load associated with the one pixel unit, resetting a voltage level at a gate of the transistor to a reference voltage, establishing a compensation voltage associated with a threshold voltage of the transistor at a first terminal of the transistor, storing data associated with the EL device in the first capacitor and maintaining a voltage level at the first terminal by a second capacitor in the impedance load, and passing a current through the EL device via the transistor, the current having a magnitude independent of the threshold voltage of the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a block diagram of an electroluminescent (EL) display, in accordance with an embodiment.

FIG. 2 is a circuit diagram of a circuit for voltage compensation in the EL display illustrated in FIG. 1, in accordance with an embodiment.

FIGS. 3A, 3B and 3C are diagrams showing a method of operating the circuit illustrated in FIG. 2 in a first phase, in accordance with some embodiments.

FIGS. 4A, 4B and 4C are diagrams showing a method of operating the circuit illustrated in FIG. 2 in a second phase, in accordance with some embodiments.

FIGS. 5A, 5B and 5C are diagrams showing a method of operating the circuit illustrated in FIG. 2 in a third phase, in accordance with some embodiments.

FIGS. 6A and 6B are circuit diagrams of a circuit for voltage compensation in the EL display 10 illustrated in FIG. 1, in accordance with another embodiment.

FIG. 6C is a timing diagram of the control signals for operating the circuit illustrated in FIG. 6A, in accordance with some embodiments.

FIG. 7 is a flow diagram showing a method of voltage compensation in an electroluminescent display.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

In the below description, a signal is asserted with a logical high value to activate a corresponding device when the device is active high. In contrast, the signal is deasserted with a low logical value to deactivate the corresponding device. When the device is active low, however, the signal is asserted with a low logical value to activate the device, and is deasserted with a high logical value to deactivate the device.

FIG. 1 is a block diagram of a display 10, in accordance with an embodiment. The display 10 may include an electroluminescent (EL) display, for example, an active matrix organic light emitting diode (AMOLED) display.

Referring to FIG. 1, the display 10 includes an active area 12, a gate driver 14 and a source driver 15. The active area 12 includes an array of pixel units P arranged in, for example, an N×M matrix. The gate driver 14 provides control signals SN and EM through N scan lines to the N rows of pixel units. The source driver 15 provides data to a selected pixel of the M columns of pixel units through data lines DATA[1] to DATA[M]. In addition, each of the data lines DATA[1] to DATA[M] is selectively coupled to a corresponding current sink I0 via a switch SW. Moreover, a power driver 16 provides supply voltages in a power rail of VDD and VSS to the active area 12. In an embodiment, VDD is approximately five volts (5V), and VSS is approximately −5V.

Each of the pixel units P in the active area 12 includes three sub-pixel units 20, which may be used to display color red (R), color green (G) and color blue (B). In other embodiments, for example, in a sub-pixel rendering (SPR) sensor, the number of sub-pixel units is not limited to three. In the present embodiment, the three sub-pixels 20 are arranged along the row direction. Accordingly, the number of data lines for the source driver 15 is 3×M.

FIG. 2 is a circuit diagram of a circuit 200 for voltage compensation in the EL display 10 illustrated in FIG. 1, in accordance with an embodiment. Referring to FIG. 2, the circuit 200 includes an exemplary sub-pixel unit 20, an impedance load 25, a switch SW and a current sink I0.

The sub-pixel unit 20 is configured in a 4T1C structure that includes four transistors and a capacitor. However, the sub-pixel unit 20 is not limited to the 4T1C structure or any specific structures. A sub-pixel unit that includes other number of transistors or capacitors may also fall within the contemplated scope of the present disclosure. In the present embodiment, the sub-pixel unit 20 includes an EL device 28, transistors T1 to T4 and a capacitor Cst. The EL device 28 includes, for example, a current-driven element that may include an organic light emitting diode (OLED), a micro LED or a quantum dot LED (QLED). The capacitor Cst serves as a storage capacitor. The transistor T3 serves as a driving transistor to drive the EL device 28 according to data stored in the capacitor Cst. In addition, each of the transistors T1 to T4 includes an n-type thin film transistor (TFT) or an n-type metal-oxide-semiconductor (NMOS) transistor.

In the exemplary 4T1C structure, a gate of the transistor T1 receives a first control signal SN on a corresponding gate line from the gate driver 14. A drain of the transistor T1 receives data (labeled “DATA”) on a corresponding data line from the source driver 15 in response to the first control signal SN. In addition, a gate of the transistor T3 is coupled to a source of the transistor T1 and to a first end of the capacitor Cst. A source of the transistor T3 is coupled to a second end of the capacitor Cst and to an anode of the EL device 28. Persons having ordinary skill in the art will understand that drain and source terminals of a MOS transistor may be interchangeable, depending on voltage levels applied thereto.

In addition, a gate of the transistor T4 receives a second control signal EM. A drain of the transistor T4 receives a supply voltage VDD. A source of the transistor T4 is coupled to a drain of the transistor T3. Further, a gate of the transistor T2 also receives the first control signal SN. A source of the transistor T2 is coupled to the source of the transistor T3 and hence the second end of the capacitor Cst as well as the anode of the EL device 28. A cathode of the EL device 28 receives another supply voltage VSS. Moreover, a drain of the transistor T2 is coupled to the impedance load 25.

The impedance load 25 associated with the exemplary sub-pixel unit 20 is formed by a network of parasitic resistors and parasitic capacitors. These parasitic resistors and capacitors may exist in or between conductive layers and dielectric layers that routing of the sub-pixel unit 20 may concern. For example, a pair of parasitic Ry and Cy is associated with a y-th sub-pixel unit in the N×M pixel array, y being a natural number between 1 and N. As a result, as viewed from the drain of the transistor T2, parasitic pairs R1, C1 to R_(N), C_(N) associated with the sub-pixel unit 20 are connected in parallel, while in each pair such as the pair R1, C1 the resistor R1 and the capacitor C1 are connected in series. The impedance load 25 can be reduced to an equivalent circuit 250, illustrated in FIGS. 3B, 4B and 5B, formed by an equivalent resistor Rcol and an equivalent capacitor Ccol. The resistance of the equivalent resistor Rcol and the capacitance of the equivalent capacitor Ccol can be simulated in a design stage when a layout of the EL display 10 is available.

The switch SW is configured to selectively electrically connect a corresponding sub-pixel unit 20 to a corresponding current sink I0, or electrically disconnect the corresponding sub-pixel unit 20 from the corresponding current sink I0. As a result, when the switch SW is closed, a current sink path between the corresponding sub-pixel unit 20 and the corresponding current sink I0 is established. In contrast, when the switch SW is released, a current sink path between the corresponding sub-pixel unit 20 and the corresponding current sink I0 is cut off. In an embodiment, the switches SW are formed by TFTs on a display panel and are external to the pixel array. In another embodiment, the switches SW are formed by MOS transistors that are integrated with the pixel array in an IC.

Each of current sinks I0 provides a constant current also denoted as I0. In some embodiments, the magnitude of current I0 is adjustable to enhance the performance of a current sink due to manufacturing factors.

The 4T1C circuit structure of the sub-pixel unit 20 is relatively simple. In addition, the circuit that may be external to the pixel array of the EL display 10 includes the switches SW and the current sinks I0, which is also relatively simple and facilitates a layout design of the active area 12. Effectively, an EL display 10 based on the above-mentioned structure is advantageous for a high pixel-per-inch (ppi) application. Moreover, the impedance load 25 can be predetermined during a design stage, and the switches and SW and current sources I0 can be easily implemented. As a result, the burden of a driver IC can be alleviated.

FIGS. 3A, 3B and 3C are diagrams showing a method of operating the circuit 200 illustrated in FIG. 2 in a first phase, in accordance with some embodiments.

Referring to FIG. 3A, controls signal EM, SN and ISW are configured to be active high in view of the n-type transistors T1 to T4. The switch SW, which includes an n-type transistor, is controlled by the control signal ISW. In operation, at time t1, the first control signal SN is asserted at a rising edge, while the second and third control signals EM and ISW stay at a high logical level. As a result, referring to FIG. 3B, all the transistors T1 to T4 are turned on and the switch SW is closed. Since the transistor T1 is turned on, a voltage level at a gate of the driving transistor T3, denoted as VG, is pulled to Vdata, which is Vref at time t1. In an embodiment, Vref is approximately 0V. Further, since the switch SW is closed, the circuit is configured to sink current via the impedance load 250 in the first phase. A current Ids flows from VDD via the transistors T4, T3, T2, the impedance load 250 and the switch SW to the current sink I0. The current Ids flowing through the driving transistor T3 can be expressed in equation (1) below.

Ids=k×(VGS−Vth3)²  equation (1)

where k is a constant, VGS represents a gate-to-source voltage of the transistor T3, and Vth3 represents a threshold voltage of the transistor T3.

Since Ids equals I0, equation (1) is rewritten in equation (2) as follows.

I0=k×(VG−VS−Vth3)² =k×(Vov)²  equation (2)

where Vov, defined as VGS−Vth3, represents an overdrive voltage of the transistor T3. Since Vov=VG−VS−Vth3 and VG=Vref. VS can be written as follows.

VS=VG−Vov−Vth3=Vref−Vov−Vth3  equation (3)

As a result, during the first phase, VG is reset to Vref, while VS is a function of Vth3. A compensation voltage, Vth3, is established at the source of the transistor T3. The relationship between VG and VS of the driving transistor T3 with respect to VDD and VSS in the first phase is shown in FIG. 3C.

FIGS. 4A, 4B and 4C are diagrams showing a method of operating the circuit 200 illustrated in FIG. 2 in a second phase, in accordance with some embodiments.

Referring to FIG. 4A, at time t2, the second control signal EM is deasserted at a falling edge, while the first control signal SN stays at a high logical level and the third control signal ISW has been deasserted. As a result, referring to FIG. 4B, the transistor T4 is turned off (shown by a cross sign “x” labeled), while the transistors T1 and T2 are kept at an on state, and the switch SW is released. Since the transistor T1 stays turned on, data D[y] is written to VG. Accordingly, VG is Vdata. As VD changes from Vref to Vdata, by function of the capacitors Cst and Ccol, VS is expressed in equation (4) below.

$\begin{matrix} {{VS} = {{Vref} - {Vov} - {{Vth}\; 3} + \left\lbrack {\left( \frac{Cst}{{Cst} + {Ccol}} \right) \times \left( {{Vdata} - {Vref}} \right)} \right\rbrack}} & {{equation}\mspace{14mu} (4)} \end{matrix}$

Where Cst and Ccol also represent the capacitances of the storage capacitor Cst and the equivalent capacitor Ccol, respectively.

The capacitance Ccol is remarkably larger than Cst, and may be hundreds of times of Cst. Accordingly, the term

$\left( \frac{Cst}{{Cst} + {Ccol}} \right)$

approaches zero and is negligible. Also, VS is substantially equal to that at the first phase, VS=Vref−Vov−Vth3, as expressed in equation (3). During the second phase, the data D[y] including information on the gray level of EL device 28 is written to VG. The relationship between VG and VS of the driving transistor T3 with respect to VDD and VSS in the second phase is shown in FIG. 4C. Note that in the second phase VGS=Vdata−(Vref−Vov−Vth3)=Vov+Vth3+Vdata−Vref, which is greater than the threshold voltage |Vth_EL| of the EL device 28. However, since the transistor T4 is turned off, no current flows through the EL device 28.

As a result, during the second phase, a data associated with the EL device 28 is stored in the capacitor Cst. Moreover, VS is maintained substantially identical to that in the first phase by means of the capacitor Ccol in the impedance load 250.

FIGS. 5A, 5B and 5C are diagrams showing a method of operating the circuit 200 illustrated in FIG. 2 in a third phase, in accordance with some embodiments.

Referring to FIG. 5A, at time t3, the second control signal EM is asserted at a rising edge, while the first control signal SN has been deasserted. As a result, referring to FIG. 5B, the transistors T1 and T2 are turned off. By the coupling function of the capacitor Cst, VG and VS are shifted by a positive value Vshift to reach an electrical equilibrium. VG and VS can be expressed in equation (5) and equation (6), respectively.

VG=Vdata+Vshift  equation (5)

VS=Vref−Vov−Vth3+Vshift  equation (6)

Accordingly, as both VG and VS being raised by Vshift, VGS is kept unchanged and, as previously discussed in the operation of the second phase, is greater than |Vth_EL|. The relationship between VG and VS of the driving transistor T3 with respect to VDD and VSS in the third phase is shown in FIG. 5C. With the control signal EM being asserted, a current Ie1 flows from VDD to VSS via transistors T4, T3 and the EL device 28, causing the EL device 28 to emit light according to the data. The current Ie1 is expressed in equation (7) below.

Ie1=k×(VGS−Vth3)² =k×(Vov+Vdata−Vref)²  equation (7)

Since the current Ie1 in equation (7) is free of any Vth term, display quality of the EL display 10 is enhanced.

As a result, during the third phase, the capacitor Ccol facilitates VG and VS to reach an electrical equilibrium and maintains VGS to be identical to that in the second phase.

FIG. 6A is a circuit diagram of a circuit 600 for voltage compensation in the EL display 10 illustrated in FIG. 1, in accordance with another embodiment.

Referring to FIG. 6A, the circuit 600 is similar to the circuit 200 described and illustrated with reference to FIG. 2 except that, for example, p-type TFTs or PMOS transistors in an exemplary sub-pixel unit 60 replace the n-type TFTs or NMOS transistors T1 to T4 in the sub-pixel unit 20 in FIG. 2. In addition, similarly, the impedance load 25 can be reduced to an equivalent load 250 as illustrated in FIG. 6B.

In the exemplary 4T1C sub-pixel unit 60, a gate of the transistor T1 receives a first control signal SN on a corresponding gate line from the gate driver 14. A source of the transistor T1 receives data on a corresponding data line from the source driver 15 in response to the first control signal SN. In addition, a gate of the transistor T3 is coupled to a drain of the transistor T1 and to a first end of the capacitor Cst. A source of the transistor T3 is coupled to a second end of the capacitor Cst and to a cathode of the EL device 28.

In addition, a gate of the transistor T4 receives a second control signal EM. A drain of the transistor T4 receives a supply voltage VSS. A source of the transistor T4 is coupled to a drain of the transistor T3. Further, a gate of the transistor T2 also receives the first control signal SN. A drain of the transistor T2 is coupled to the source of the transistor T3 and hence the second end of the capacitor Cst as well as the cathode of the EL device 28. An anode of the EL device 28 receives another supply voltage VDD. Moreover, a source of the transistor T2 is coupled to the impedance load 25.

FIG. 6C is a timing diagram of the control signals EM, SN and ISW for operating the circuit illustrated in FIG. 6A, in accordance with some embodiments.

Referring to FIG. 6C, the control signals EM, SN and ISW are similar to those described and illustrated with reference to FIG. 3A, 4A or 5A except that, for example, the control signals EM, SN and ISW in FIG. 6C are active low or asserted at a falling edge in view of the p-type transistors T1 to T4 in the sub-pixel unit 60. As shown in FIG. 6B, a current Ie1′ flows from VDD to VSS via the EL device 28 and the transistors T3, T4, causing the EL device 28 to emit light according to the data. The current Ie1′ is expressed in equation (8) below.

Ie1′=k×(|VGS|−|Vth3|)² =k×(Vov+Vdata−Vref)²  equation (8)

Since the current Ie1′ in equation (8) is free of any Vth term, display quality of the EL display 10 is enhanced.

FIG. 7 is a flow diagram showing a method of voltage compensation in an electroluminescent display.

Referring to FIG. 7, in operation 71, an electroluminescent (EL) display is provided. The EL display includes an array of pixel units each including an EL device, a transistor and a first capacitor.

Next, in operation 73, one of the pixel units is selectively connected to a current sink via an impedance load associated with the one pixel unit.

In operation 75, a voltage level at a gate of the transistor is reset to a reference voltage during a first phase.

In operation 76, a compensation voltage associated with a threshold voltage of the transistor is established at a first terminal of the transistor during the first phase.

In operation 77, a data associated with the EL device is stored in the first capacitor during a second phase. In addition, a voltage level at the first terminal of the transistor during the second phase is maintained substantially identical to that in the first phase by means of a second capacitor in the impedance load. Moreover, the capacitor Ccol facilitates the voltage levels at the gate and the first terminal of the transistor to reach an electrical equilibrium and maintains the gate to source voltage to be identical to that in the second phase.

Subsequently, in operation 78, a current is passed through the EL device via the transistor. The current has a magnitude independent of the threshold voltage the transistor.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A circuit for voltage compensation in an electroluminescent (EL) display, the circuit comprising: a pixel unit of the EL display, the pixel unit including: an electroluminescent (EL) device; a first capacitor configured to store a data associated with the EL device; and a transistor including a gate coupled to a first end of the first capacitor, and a first terminal coupled to a second end of the capacitor; an impedance load associated with the pixel unit, the impedance load including a second capacitor having a capacitance remarkably larger than that of the first capacitor; and a switch to selectively connect the pixel unit to a current sink via the impedance load.
 2. The circuit according to claim 1, wherein the pixel unit further includes a transistor configured to reset a voltage level at the gate of the transistor during a first phase.
 3. The circuit according to claim 2, wherein the transistor is configured to receive a data associated with the EL device during a second phase.
 4. The circuit according to claim 3, wherein the second capacitor is configured to maintain a voltage level at the first terminal of the transistor in the second phase substantially identical to that in the first phase.
 5. The circuit according to claim 3, wherein the pixel unit further includes another transistor configured to pass a current through the EL device during a third phase.
 6. The circuit according to claim 5, wherein the second capacitor is configured to maintain a voltage difference between the gate and the first terminal of the transistor in the third phase substantially identical to that in the second phase.
 7. The circuit according to claim 5, wherein the current has a magnitude independent of the threshold voltage of the transistor.
 8. The circuit according to claim 2, wherein the pixel unit further includes another transistor configured to establish at the first terminal of the transistor a compensation voltage associated with a threshold voltage of the transistor during the first phase.
 9. The circuit according to claim 8, wherein the another transistor includes a terminal, and the switch is configured to selectively connect the terminal to the current sink via the impedance load.
 10. An electroluminescent (EL) display, comprising: an array of pixel units, and a circuit for voltage compensation for the pixel units, the circuit comprising: a pixel unit of the EL display, the pixel unit including: an electroluminescent (EL) device; a first capacitor configured to store a data associated with the EL device; and a transistor including a gate coupled to a first end of the first capacitor, and a first terminal coupled to a second end of the capacitor; an impedance load associated with the pixel unit, the impedance load including a second capacitor having a capacitance remarkably larger than that of the first capacitor; and a switch to selectively connect the pixel unit to a current sink via the impedance load.
 11. The EL display according to claim 10, wherein the pixel unit further includes a transistor configured to reset a voltage level at the gate of the transistor during a first phase.
 12. The EL display according to claim 11, wherein the transistor is configured to receive a data associated with the EL device during a second phase.
 13. The EL display according to claim 12, wherein the second capacitor is configured to maintain a voltage level at the first terminal of the transistor in the second phase substantially identical to that in the first phase.
 14. The EL display according to claim 12, wherein the pixel unit further includes another transistor configured to pass a current through the EL device during a third phase.
 15. The EL display according to claim 14, wherein the second capacitor is configured to maintain a voltage difference between the gate and the first terminal of the transistor in the third phase substantially identical to that in the second phase.
 16. The EL display according to claim 14, wherein the current has a magnitude independent of the threshold voltage of the transistor.
 17. The EL display according to claim 11, wherein the pixel unit further includes another transistor configured to establish at the first terminal of the transistor a compensation voltage associated with a threshold voltage of the transistor during the first phase.
 18. The EL display according to claim 17, wherein the another transistor includes a terminal, and the switch is configured to selectively connect the terminal to the current sink via the impedance load.
 19. The EL display according to claim 18 further comprising a transistor configured to reset a voltage level at the gate of the transistor in response to the first control signal.
 20. A method of voltage compensation in an electroluminescent (EL) display that comprises an array of pixel units each including an EL device, a transistor and a first capacitor, the method comprising: providing a switch to selectively connect one of the pixel units to a current sink via an impedance load associated with the one pixel unit; resetting a voltage level at a gate of the transistor to a reference voltage; establishing a compensation voltage associated with a threshold voltage of the transistor at a first terminal of the transistor; storing data associated with the EL device in the first capacitor and maintaining a voltage level at the first terminal by a second capacitor in the impedance load; and passing a current through the EL device via the transistor, the current having a magnitude independent of the threshold voltage of the transistor. 